`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:04:29 04/19/2014 
// Design Name: 
// Module Name:    VGA_CPU_TOP 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module VGA_CPU_TOP(signal,red, green, blue, HS, VS, led, sound_led,
						 clk, reset, resume_button, clk_key, data_key,
						 speaker, gain, shutdown);
						 
input [3:0] signal;
input clk, reset, resume_button, clk_key, data_key;
output [1:0] blue;
output [2:0] green, red;
output HS, VS, speaker, gain, shutdown;			
output [5:0] led;
output [1:0] sound_led;			 

//////////////
// internals
//////////////

wire px_clk;
wire dummy_credits;
assign dummy_credits = 0;
wire [10:0] hcounter, vcounter;
wire blank;

/*wire [21:0] O_Player1;
wire [10:0] O_Score;
wire [362:0] O_Line1;
wire [362:0] O_Line2;
wire [362:0] O_Line3;
wire [362:0] O_Line4;
wire [362:0] O_Line5;
wire [43:0] O_Shield;
wire [32:0] O_Player1_bullet;
wire [32:0] O_RS_bullet;
wire [32:0] O_PS_bullet;
wire [32:0] O_SS_bullet;
wire [21:0] O_Bonus;*/



wire [15:0] R0,R1,R2,R3,R4,R5,R6,R7;
wire [11:0]pc;
wire [15:0] selection;
wire [3:0] aud_line;
wire cpu_clk1,cpu_clk2,cpu_clk3,cpu_clk4,cpu_clk_in,switch1,switch2, switch3, switch4;

wire [12:0] P1_Out;
wire [21:0] Alien_Pos;
wire [21:0] Alien_Status;
wire [22:0] P1_Bullet;
wire [22:0] Alien_Bullet;
wire [11:0] Bonus_Out;
wire [10:0] Score;
wire [7:0] Shields_Out;
//wire [6:0] signal;

assign cpu_clk_in = (signal == 0) ? cpu_clk1:
					     (signal == 1) ? cpu_clk2:
						  (signal == 2) ? cpu_clk3:
						  cpu_clk4;

assign sound_led = aud_line[1:0];

//choose
assign selection = (signal == 0) ? R0:
						 (signal == 1) ? R1:
						 (signal == 2) ? R2:
						 (signal == 3) ? R3:
						 (signal == 4) ? R4:
						 (signal == 5) ? R5:
						 (signal == 6) ? R6:
						 (signal == 7) ? R7:
						  {4'd0,pc};
						  
//////////////
// modules
//////////////

CLK_div25MHz C0(px_clk,clk);
CLK_CPU #(8) C1(cpu_clk1,clk);
CLK_CPU #(10) C2(cpu_clk2,clk);
CLK_CPU #(12) C3(cpu_clk3,clk);
CLK_CPU #(14) C4(cpu_clk4,clk);

TOP T0(R0,R1,R2,R3,R4,R5,R6,R7,pc,cmp_flag,
			P1_Out, P1_Bullet, Alien_Pos, Alien_Status, Bonus_Out, Score, Shields_Out,
			led,
			vid_line,aud_line,poll_line, 
			cpu_clk_in,reset,resume_button,clk_key, data_key,Alien_Bullet);
		 
//sprite_display S0(red, green, blue, hcounter, vcounter, video_out[10:0], blank, px_clk, dummy_credits, dummy_credits);		 

sprite_display S0(red, green, blue, hcounter, vcounter, blank, px_clk, inccredit, deccredit, P1_Out, Alien_Pos, Alien_Status, P1_Bullet, Bonus_Out, Score, Shields_Out,Alien_Bullet);

VGA_controller V0(px_clk,HS,VS,hcounter,vcounter,blank);
	
	
//Rui, these might need to be altered	
assign switch1 = aud_line[0];
assign switch2 = aud_line[1];
assign switch3 = aud_line[2];
assign switch4 = aud_line[3];	
music m0(speaker, gain, shutdown, clk, switch1, switch2, switch3, switch4);	

//reg test
//TOP_VGA VGA (HS,VS,red,green,blue,clk,selection);

endmodule
